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Proceedings of CAD'14, 2014, 100-102
3D ICs Layout Hypergraph Representation

Katarzyna Grzesiak-Kopeć, Maciej Ogorzałek, Jagiellonian University

Abstract. According to Moore’s Law, the number of elements in a typical integrated circuit design (IC) doubles approximately every two years. The task of 3D ICs floorplanning involves the assembly of millions of elements and is an enormous intellectual challenge. It relates not only to topological arrangement of components but also appropriate wiring of circuit elements to fulfill different power, timing and manufacturability requirements. No wonder that the importance of electronic design automation (EDA) tools rapidly increases. Graphical and geometric data describing layout design is not enough to support the computer control of the design process. In order to automatically generate valid design solutions that meet requirements and fulfill constraints, the design knowledge representation is needed. Generally, either symbolic or graphical knowledge description may be applied. In the first case, facts are symbolic terms and the process of inferring involves the manipulation of these terms. In the second one, the spatial relations between components determine the structure of knowledge representation and the way it is exploit. The latter approach can be naturally adopted as a 3D ICs layout representation. This paper presents a knowledge intensive 3D ICs layout representation in the form of hypergraphs.

Keywords. Hypergraphs, 3D ICs, optimization, 3D layout design

DOI: 10.14733/cadconfP.2014.100-102